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Logic design of NAND(NOR) circuits by the entered-map-factoring method
Journal article   Peer reviewed

Logic design of NAND(NOR) circuits by the entered-map-factoring method

A.M. Rushdi
Microelectronics and reliability, Vol.27(4), pp.693-701
1987
DOI: https://doi.org/10.1016/0026-2714(87)90016-3

Abstract

This paper presents an entered-map version of the map factoring method for the logic design of NAND(NOR) circuits. The new version has a better variable-handling capability as well as pedagogical advantages. It is demonstrated by several examples, and is reported to have a favourable students' response.

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