Abstract
Clock recovery circuits are used in data communication systems for the system synchronization. In general a PLL (Phase Locked Loop) circuit is used to extract the clock signal from the input data stream. The recovered clock signal is always jittered and have to be adjusted by using a dejitter circuit. Tracking these errors over an extended period of time determines the system stability. Sources of jitter in PLL circuit itself are due to some ac components at the VCO (Voltage Controlled Oscillator) input which modulate its output frequency. A narrow band PLL may be used after the recovery circuit to minimize the jitter associated with the recovered clock. This second PLL has to be locked at the same frequency as the recovered clock. Other solution is by using a single PLL with Voltage Controlled Crystal Oscillator (VCXO) whose centre frequency is equal to the data bit rate followed by a wide band loop filter. The conversion gain of the VCXO (Hz/V) is very small so a narrow band PLL is resulted without sacrificing the dynamic behaviour. This work presents a proposed system for low jitter clock recovery circuit using two cascaded PLLs which enables to generate several clock frequencies using single VCXO. The proposed described is simulated and verified experimentally. The experimental results confirm the simulation.