Abstract
This paper presents new low-power, high-speed unified and scalable word-based radix 8 architecture for Montgomery modular multiplication in GF(P) and GF(2 (n) ). This architecture has some similarities to the architecture of Huang, but it achieves more reduction in area and power consumption. To speed up the modular multiplication process, the hardware architecture employs carry-save addition to avoid carry propagation at each addition operation of the add-shift loop. To reduce power consumption, some latches called glitch blockers are employed at the outputs of some circuit modules to reduce the spurious transitions and the expected switching activities of high fan-out signals in the architecture. Also, we proposed a modified low-power dual-field 4-to-2 carry-save adder that has internal logic structure that reduces the chance of glitches occurrence. An ASIC implementation of the proposed architecture shows that it can perform 1,024-bit modular multiplication (for word size w = 32) in about 5.45 mu s. Also, the results show that it has smaller Area x Time values compared to all unified and scalable designs by ratios ranging from 12.2 to 66.8 %, which makes it suitable for implementation where both area and performance are of concern. Also, it has higher throughput over them by ratios ranging from 6.0 to 80.7 %. In addition, it achieves a decrease in power consumption compared to these designs by ratios ranging from 18.8 to 52.6 %. By comparing to the designs that are not unified, it has slightly higher Area x Time and lower throughput values compared to some of them. However, it achieves a significant low-power consumption compared to all of them.