Abstract
Electron cyclotron resonance
Cl
2
/Ar
plasma etching characterization was performed to obtain low damage and low surface roughness conditions for GaInP lattice matched to GaAs. Micro-Raman spectroscopy, atomic force microscopy (AFM) and surface profiling were used to characterize the near-surface quality and etch rate of GaInP. The results show that near-surface damage increases with dc self-bias voltage in both Ar and
Cl
2
/Ar
plasmas. Etching in pure Ar plasma results in significant increase in the transverse-optic (TO) intensity at high dc self-bias voltage of 50 and 70 V, with the longitudinal-optic (LO) peaks downshifted in frequency. A normalized LO/TO intensity was quantified in this study to represent the combined effect of increase in TO intensity and slight decrease in LO intensity. In the case of
Cl
2
/Ar
plasma, substantial shifting of the GaP-like LO peak position to lower frequency was observed at dc self-bias voltage of 70 V at 120 °C with increase in the TO peak intensity. In addition, the decreasing trend of the normalized LO/TO intensity of GaP-like LO and InP-like LO peak was observed for samples etched under dc self-bias voltages of 40–70 V. Both observations from
Cl
2
/Ar
plasma etching indicate the alteration of the GaInP near-surface region by etch induced damage within the dc self-bias voltage range of 40 to 70 V. AFM studies showed surface damage consistent with the change in Raman spectrum. The damaged layer was caused by enhanced physical etching, which may result in
InCl
x
formation and therefore etch rate fluctuation at 70 V. The Raman spectrum of the sample etched at 30 V dc self-bias voltage was similar to that of the reference spectrum with normalized LO/TO intensity values comparable to that of the reference values, indicating a low damage process with root-mean-square (rms) surface roughness of 5.5 nm. Substrate temperature dependence of the surface roughness was studied at 20 V dc self-bias voltage. At 110 °C and 20 V dc self-bias voltage, desorption of volatile products results in low rms surface roughness of 1.28 nm and slow etch rate of 0.4 nm/s. The 20 V dry etch process was compared favorably to a HCl-based wet etch process. The low damage, low surface roughness and low etch rate process has excellent potential in compound semiconductor device processing, such as for GaInP emitter layer etching in heterojunction bipolar transistors fabrication.