Abstract
In the modern System on Chip (SoC)-based designs, embedded memory occupies the majority of the area. Therefore, the demand for fast self-testing plays a vital role in the SoC device as its memory density increases. The focus of this research study is to provide a self-testing mechanism integrated with the SoC design for fault diagnosis and failure analysis. In particular, this paper proposes a controller design to test memories at SoC devices, called a memory built-in self-test (MBIST) controller. This controller works on the principle of the proposed March-ee (enhanced elements) algorithm with the primary objective to improve the test speed, fault coverage, and power consumption at a low area overhead. The complete design of the MBIST controller with the associated March-ee algorithm is minimal and easy to be integrated into any SoC device to provide a vibrant feature of memory fault detection. The results obtained are compared with that provided by the existing March algorithms, using the same design specifications, where the proposed March-ee MBIST controller has shown better results in terms of power consumption, fault coverage, timing, and area.