Abstract
Model Based System Engineering (MBSE) is a renowned approach in the context of embedded systems development. It is frequently used to deal with the structural and behavioral aspects of system design. However, the verification of system design is generally performed in isolation. It is particularly true in the context of assertion based verification. Consequently, there is a huge gap between system design and its verification that seriously effects the productivity and time-to market objectives. Therefore, in this research, we target to reduce this gap by exploiting the features of MBSE and SystemVerilog assertions (SVA's). This article introduces a novel MBSE approach to model the design verification aspects of embedded systems, along with the system design (structural and behavioral aspects). We propose SystemVerilog in Object Constraint Language (SVOCL), an OCL temporal extension for SystemVerilog, to represent the design verification requirements by means of SVA's. As a part of research, SVOCL transformation engine has been developed to generate SVA's code in order to automate the design verification of embedded systems. The application of SVOCL has been validated through four case studies.