Abstract
SiGe/Si resonant tunneling diodes (RTDs) grown on relaxed n-Ge
0.3Si
0.7 virtual substrates are attractive devices for low-power/high-frequency applications compatible with Si-CMOS technology. With the intention to improve the performances of n-type RTDs build-on Si
0.4Ge
0.6/Si/Si
0.4Ge
0.6 double barriers, we consider graded Si
1−
x
Ge
x
(
x=0.3→0.0) spacers (triangular quantum wells) for injection and collection of electrons. Graded layer composition, implanted for the lattice mismatch growth of many semiconductors, has offered significant improvement in the epilayer quality and hence was used for many advanced electronic and optoelectronic applications. The modeled design is aimed to further reduce the voltage at which peak-current density is achieved and to increase the current-peak to valley ratio. We report a numerical solution of the conduction-band profile by solving self-consistently Schrödinger and Poisson equations without and with an applied electric field. An analysis of the Stark effect on electronic levels is made. Two main features have been extrapolated: (i) a charge transfer can occur due to the tunneling effect, and this charge transfer tends to saturate as the applied electric field increases; (ii) the middle quantum well is populated compared with common RTD having an abrupt Si spacer (squared quantum wells).