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NOVEL CMOS SAMPLED-DATA VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS
Journal article   Peer reviewed

NOVEL CMOS SAMPLED-DATA VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS

S E Rehan and M I Elmasry
Electronics letters, Vol.28(13), pp.1216-1218
18/06/1992
DOI: https://doi.org/10.1049/el:19920768

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
A mixed-mode VLSI implementation of artificial neural networks offers a tradeoff solution for speed, area saving, and flexibility. In the Letter, a novel CMOS sampled-data programmable synapse and a simple CMOS analogue neuron have been developed. Using a 1.2-mu-m CMOS technology, the synapse consumed 120 x 120-mu-m2 and the neuron consumed 120 x 260-mu-m2.

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