Abstract
Images and videos are characterized by the great mass of information that they convey which causes a problem in transmitting high quality video streams over a network or store them with good quality and low bandwidth. High Efficiency Video Coding (HEVC) is the latest video coding technology which differs from the previous video coding technologies by reducing data size up to 50% with significantly higher video quality. The transform module is very complex in terms of computational effort, a hardware implementation on reconfigurable circuit is crucial for the requirement of different real time multimedia applications. In this paper, we present novel hardware architecture for real time implementation of transform algorithm used in HEVC. This equipment is intended to be utilized as a major aspect of an entire HEVC video coding framework for video meeting applications. This design is actualized in VHDL and synthesized on Xilinx Spartan 3E FPGA. The VHDL code can work at 330 MHz for the 4 x 4 Transform, 275 MHz for 8 x 8 transform and 200 MHz for 16x16 transform. This design presents least of inactivity and most extreme of throughput and full use of equipment assets.