Abstract
Networks-on-Chip (NoCs) provides a packet-based communication model for the System-on-Chip (SoC) architecture to achieve objectives of lower power, higher performance and optimized area. To evaluate NoC performance and explore architectural design options, synthetic traffic models provide better solution in terms of simulation flexibility and faster simulation. In this synthetic traffic, models are generated for the simulation to optimize the computational resources requirements which will be placed inside NoC's architecture before the early design process. In this paper, Wavelet-based Rosenblatt synthetic traffic [RST] is designed and examined which is a non-Gaussian process based on the 2nd-order Hermite Process. The proposed traffic is applied to SPLASH-2 benchmarks and compared with Gaussian and Non-Gaussian traffic on the parameters of latency, power and buffer-loss. We applied the synthetic traffic on multicore architecture to capture parameters which would be helpful for network designers to choose optimized network resources during the early design architecture. We demonstrate our traffic model: first, how it can be used to describe and acquire non-gaussian burstier traffic on NoC; second, how it can be used to produce synthetic traffic traces that can drive exploration of the early design space for NoCs. Our traffic model helps the chip network designer to choose optimized queue storage inside the router in early design process.