Abstract
P-type 4H-SiC layers formed by ion implantation need high temperature processes, which generate surface roughness, losing and incomplete activation of dopants. Due to dopant redistribution and channeling effect, it is difficult to predict the depth of the formed junctions. Vapor-Liquid-Solid (VLS) selective epitaxy is an alternative method to obtain locally highly doped p-type layers in the 1020 cm-3 range or more. The depth of this p-type layers or regions is accurately controlled by the initial Reactive-Ion-Etching (RIE) of the SiC. Lateral Junction Field Effect Transistor (JFET) devices are fabricated by integrating p-type layers created by Al ion implantation or VLS growth. The p-type VLS layers improve the access resistances on the electrodes of the fabricated devices.