Abstract
Modular inverse is a division operation performed over a modulus and is considered as a fundamental operation for many public-key cryptosystems. Extended Euclidean Algorithm (EEA) is considered one of the most efficient algorithms to compute the modular multiplicative inverse of two coprime numbers. In this paper, we are reporting on the FPGA implementation of 128-bit modular inverse unit using Extended Euclidean Algorithm (EEA) algorithm with maximum possible parallelism of the internal operations. To verify the deposed implementation, we have synthesized our VHDL coding using ALTERA Cyclone IV FPGA with target device EP4CGX22CF19C7 using Quartus II simulation package. The experimental results showed that the proposed implementation recorded a critical path delay of 16.84 ns with maximum operational frequency of 72.7 MHz. Also, the area of the proposed design was estimated as the number of logic elements (LEs) utilized by the proposed unit which is reported as 7157 LEs. Finally, the power dissipation of the proposed using was estimated as the total FPGA thermal power dissipation and reported as 231.41 mW. Hence, the proposed modular inverse module can be efficiently embedded with many FPGA based cryptographic applications.