Abstract
LDPC codes are gaining attention due to their excellent performance but still there are a lot of challenges in the hardware implementation. Due to high complexity, LDPC codes generally offer high processing delays which makes them impractical for many applications. Efforts have been made to keep a good tradeoff between the complexity and performance. Quasi cyclic LDPC codes have the advantage of both encoding and decoding over the conventional LDPC (non-structured) as they reduce the hardware complexity greatly. It has simplified the check and variable node interconnections. QC LDPC has limited decoding performance compared to unstructured random LDPC codes. Different architectures have been proposed to improve the throughput as well as reduce the complexity.