Abstract
Hardware/software codesign involves various design problems, including system specification, design space exploration, hardware/software co-verification, and system synthesis. An effective codesign process requires accurately predicting the performance, cost and power consequence of any design trade-off in algorithms and hardware configuration. This paper presents a new co-design methodology called R-codesign. Based on new modeling and partitioning techniques for reconfigurable embedded systems, R-codesign creates a task allocation of SW functions and HW behaviors based on the user constraints and using heuristics. The modeling approach relies basically on probabilistic estimations of the executions of system tasks. Hardware and software specifications are the inputs of R-codesign which constructs partitions (clusters of tasks) and maps them to a specified heterogeneous multiprocessor system-on-chip execution platform with field-programmable gate array. Several design constraints are evaluated and tested during the partitioning and mapping process. We have developed a visual environment called SPEX that implements this methodology. SPEX computes a control matrix which is a pre-computation of validated mappings that will occur in a case of a system reconfiguration. SPEX is an open source, fast and provides efficient results for the codesign of reconfigurable embedded systems.