Abstract
This study details a new technique for the fast and efficient design and analysis of system level electrostatic discharge (ESD) protection strategy using developed coupling transfer impedance function. The transfer coupling characteristics from the zapping point to the victim location on a DUT can be computed using coupling transfer gain function. Subsequently, it is integrated with an ESD current source in a SPICE type circuit simulator for the fast and efficient analysis of induced ESD coupling noise and the design of the appropriate ESD protection scheme with the suitable choice of ESD protection device (diodes, SCR, GGNMOS, GCNMOS etc.). The study discusses the different protection schemes i.e. primary, secondary and double ESD protections, and the effect of the selected diode types and ESD stressing levels on the employed protection strategy. The proof-of-concept is validated through the rapid design of suitable system level ESD protection strategy for a microstrip-line PCB, high-speed mobile device memory module, and a portable notebook motherboard.