Abstract
This paper presents a novel technique for FPGA based implementation of high-resolution SAR system using UWB-OFDM architecture. Greater computation time and larger memory requirement are the main difficulties in processing large amount of raw data in real-time SAR imaging. Significant part of the computation time is related to range and azmuth compression of raw SAR data which in turns heavily depends on computing FFT, IFFT and complex multiplication. A shared memory based FPGA model is developed using Xilinx block-set that provides real-time SAR imaging with higher accuracy and less computation time. The design procedures are straightforward and can be applied to practical SAR system for real-time imaging. The model is designed as hardware co-simulation using Xilinx system generator and implemented on Xilinx Virtex-6 ML605 FPGA.