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Reconfigurable FIFO memory circuit for synchronous and asynchronous communication
Journal article   Peer reviewed

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Saleh Abdel-hafeez and Ann Gordon-Ross
International journal of circuit theory and applications, Vol.49(4), pp.938-952
04/2021

Abstract

8T‐Cell SRAM asynchronous and synchronous controlled datapath FIFO high‐speed and low‐power IoT and NoCs two‐phased clock

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