Abstract
A novel reliability-aware clock distribution network clock distribution network in a 3-D I/O interface packaging integrating memristor ratioed logic (MRL) is presented. An evolutionary algorithm has been employed to obtain the optimal reliability tradeoffs and the placement of the intertier clock delivery network. To improve the signal integrity, to increase the power efficiency, and to decrease the clock noise, through-silicon vias transfer the clock along with the power/ground links in a symmetric-centroid arrangement. The proposed reliability-aware 3-D packaging clock distribution network (CDN) can significantly decrease the clock skew/jitter and propagation delay, increase the energy efficiency, and improve the signal quality of the whole aged system. The proposed on-chip 3-D CDN architecture is analyzed and designed using a 65-nm CMOS technology at 1.0 V. The results show that the reliability and power efficiency of the proposed CDN with optimization has been significantly improved for a 15-year aged circuit. Moreover, the clock latency and the total power consumption of the proposed MRL-based CDN are improved around 10% and 22%, respectively, under process, voltage, and temperature variations.