Abstract
In power and energy applications, implementing a large number of phase-locked loops (PLLs) involves using transfer delays. These delays are employed for different control and filtering purposes, such as creating a fictitious orthogonal signal (which is required for the frame transformation in single-phase PLLs) and filtering harmonics, dc offset, and other disturbances. Depending on the application in hand and the expected variation range of the grid frequency, the length of these delays may be variable or fixed. Roughly speaking, the variable-length delays are often preferred for applications where large frequency drifts are anticipated and a high accuracy is required. To the best of authors' knowledge, the small-signal modeling of a variable-length delay-based PLL has not yet been conducted. The main aim of this paper is to cover this gap. The tuning procedure and analysis of these PLLs are also presented. As design examples, some well-known single-phase and three-phase PLLs are considered.