Abstract
In this paper, a small-area and high-efficiency single-inductor multiple output (SIMO) boost converter with digital pulse-width modulation (DPWM) is proposed. The DPWM comprises a delay line using interlaced hysteresis delay cells (IHDCs) that occupy a small area while consuming a low power amount. These proposed IHDCs are applied to replace the conventional delay cells of the prior works for both the power and area reductions. Regarding the DC-DC converter, this technique comprises fewer digital blocks in the feedback path compared with the conventional DC-DC converter, and the DPWM architecture uses IHDCs. The purpose of the digital limiter block is to concede some helpful code for the DPWM. The IHDC topology used for delay in DPWM is of the simplest architecture. The high-side power switch gate drivers need individual phases which are generated by phase control. The Complementary Metal Oxide Semiconductor (CMOS)-fabrication process is 55 nm, with a standard supply voltage of 1.8 V and outputs of 2.2 and 2.4 V. The chip area is approximately 170 x 190 mu m and its efficiency is 94.4%.