Abstract
Negative bias temperature instability in HfSiON gate dielectric based p-channel transistors has been studied at 293, 363, 398, and 433 K and the "slow trap" creation and relaxation has been investigated. Analysis of transistor characteristics suggests that slow trapping in this case is almost entirely related to positive charge trapping in the dielectric as opposed to the dielectric/semiconductor interface. A linear threshold voltage shift versus fractional mobility variation relationship is established as expected. A simplified approach is used to crudely estimate the importance of fast relaxing trapped charges and its magnitude estimated for the four temperatures studied in this work.