Abstract
Comparator hysteresis is a memory phenomenon allowing outputs maintaining their past stable states until the input difference overcomes a given threshold voltage. In some applications, such as ADCs and memories, hysteresis is a deterministic error that should be minimized In others, it can be considered as one of the design parameters, such as in implementing hysteresis control-based systems such as peak detectors and spectrum analyzers. In any case, the designer should be aware of how to estimate hysteresis to achieve the desired performances. This paper presents a mathematical approach to estimate hysteresis in clocked latch comparators. It has been demonstrated that hysteresis is not only sensitive to the clock frequency, but also to several design parameters including the transistors sizes, the common mode input voltage and the tracked input frequencies. The analysis results are validated through electrical simulations using a commercially available 0.18 mu m CMOS technology showing a maximum error of 8.6%.