Abstract
The real-time system (RTS) design is a major challenge due to the complexity of the considered application and the appearance of multiprocessor architectures. Most of the research in this area is interested in high abstraction level methods to decrease the design convolution. In particular, the Unified Modeling Language (UML) profiles and the Model Driven Engineering (MDE) aim at being an adequate solution to support the whole life cycle of RTS design with its real-time constraints and performance issues. Based on MDE and the Modeling and Analysis of Real-Time and Embedded systems (MARTE) profile, the present manuscript proposes an interactive partitioning scheduling of RTS running on multiprocessor architecture. A special attention is paid to the scheduling analysis step to accelerate the exploration of HW/SW space solution. Starting from a candidate solution modeled with UML activity and annotated with MARTE stereotypes, a mapping process to dynamic priority time Petri Nets (dPTPN) was defined. The considered dPTPN is able to prove the schedulability or provide a counterexample to determine the partitions causes of temporal fault. This counterexample presents a useful feedback to the HW/SW space solution explorer in the aim to exclude all solution containing the described partitions.