Abstract
The higher order statistics (HOS) (or cumulants), and their associated Fourier Transforms, have been established as a powerful analytical tool in modern signal processing. This paper presents a computationally efficient VLSI architecture for computing third-order cumulants. The architecture is based on the systolic array implementation and exploits parallelism, pipelining, and regular cell structures. The architecture is designed with 1.0 mum CMOS technology using the scalable design rules of MOS Integrated Services (MOSIS). The VLSI architecture contains approximately 36500 transistors and it is capable of operating at a speed of 5.2 MHz.