Abstract
Discrete Wavelet Transform (DWT) is considered among the few computationally expensive block of multimedia compression standards. In this work, we proposed a reduced hardware complexity VLSI architectures of 5/3 and 9/7 lifting bi-orthogonal DWT for multimedia applications. The architecture uses a combination of Distribute Arithmetic (DA) and Canonical Signed Digit (CSD) based implementation to reduce the hardware complexity. The resulting lifting based architecture discretely finds optimized number of sum of products to give minimum realization. The architecture is implemented on Field Programmable Gate Array (FPGA) with results compared with known classical and other optimized DWT architectures.
•A reduced hardware complexity architecture of 5/3 and 9/7 lifting bi-orthogonal DWT•Uses Distribute Arithmetic and Canonical Signed Digit to give minimum realization•Functionality verified using Altera DE2-115 Cyclon IV FPGA•Hardware results compared with other optimized DWT architectures